Scan-based design and testing has been widely adopted to reduce the cost of testing VLSI circuits. Scan-based logic diagnosis techniques have been very helpful in assisting physical failure analysis engineers to quickly root-cause defect mechanisms. A functioning scan chain is critical to test the system logic through scan-based test patterns. When there is a defect inside the scan chain logic, it is important to root-cause and fix the problem before scan test patterns can be used to test system logic.
A defect in a scan chain usually impacts scan pattern load and unload operations and causes massive failures on an ATE (automatic test equipment). During production test, usually a scan chain test pattern is applied on the circuit to check the integrity of scan chains. A scan chain test pattern can consist of scan load and scan unload operations only. The commonly used scan chain test pattern contains repeating 0011s. If a scan chain fails a scan chain test pattern, it indicates that the scan chain is not functioning properly. For a circuit that fails a scan chain test pattern, scan chain failure diagnosis technique(s) is/are typically used to identify the area of interest before physical failure analysis. One form of scan chain failure diagnosis takes a tester failure log, circuit netlist, and scan test patterns as inputs and reports a list of suspects with diagnostic scores to show the confidence that a suspect has a defect in it. Scan chain failure diagnosis is nondestructive and accurate and can make physical fault isolation much easier.
Research into scan chain failure mechanisms and their diagnosis techniques have advanced in the last decade. Hardware-based, tester-based and software-based scan chain failure diagnosis techniques have been used to isolate defects in a scan chain. While hardware-based and tester-based diagnostic techniques are very powerful in isolating scan chain defects, they are usually more expensive than software-based diagnosis techniques, either due to expensive tester time or due to expensive special design support.
Most research in the direction software-based scan chain failure diagnosis techniques uses conventional fault models including stuck-at, transition and hold-time faults to model the behavior of scan chain defects. For example, a scan cell stuck-at-0 fault usually models a defective scan cell where the output of the scan cell can only propagate a binary value “0” onto its next scan cell. These fault models have been successfully used in state of the art scan chain failure diagnosis techniques. With the advancement of manufacturing process from 90 nm to 65 nm and beyond, a significant number of manufacturing defects lie inside design library cells. The behavior of such defects is becoming more complicated and traditional fault models are no longer sufficient to model this complicated defect behavior. The complicated defect behavior has driven recent advancements in circuit testing and fault diagnosis technologies. To improve test pattern quality and defect coverage, designers have been using advanced fault models to improve test pattern quality. To improve logic fault diagnosis accuracy and precision, designers have been tracking down into design cells to find the defect location, or using more general fault models to model the behavior of a complicated defect in order to understand the behavior of the defect. Library cell internal fault reports show that some defects do not show up as perfect stuck-at faults or transition faults. Instead, the output of a library cell depends on the input combinations of a given library cell.